Prototyping with Frequency-Flexible Crystal Oscillators

Developers of new systems ideally should make decisions regarding clocking requirements early in the design process. Although clocking rates are critical parameters that should be known in
advance, determining these rates sometimes requires experimentation and re-evaluation. The ability to quickly change clock frequencies during the prototyping and validation stages of a
design can accelerate time to market.


Evaluating Multiple Frequencies

When conducting any system design effort, frequency changes often become necessary late in the design cycle. For example, experimenting with and optimizing clocking rates during the development process often leads to improved performance and a more efficient design. In other cases, a bug or miscalculation in the design may require a change in frequency.

Last-minute changes are very common, especially in FPGA-based applications. The extreme flexibility of FPGAs means that logic path widths and data rates can be quickly adapted to improve power, throughput or gate utilization. For example, changing data path width or decreasing the clock rate may be an effective way to close timing in the final stages of an FPGA design.

Frequency Margining

Systems that use standard frequencies can also benefit from frequency-flexible XOs for design validation and frequency margining during production test. Although an Ethernet MAC or PHY may specify a 156.25 MHz reference XO, a fixed-frequency reference cannot exercise rate
tolerances.

Frequency margining also can be carried out using multiple XOs and a multiplexer as shown in .The disadvantages of this scheme include the limited number of frequencies and the introduction of additional noise and phase discontinuities that occur when switching between
frequencies.

Frequency Margining Using Multiple XOs and a Multiplexer

Using external clock sources or multiple XOs to perform frequency margining often limits the designer’s ability to make fine frequency adjustments or validate a continuum of frequencies to troubleshoot suspected problem areas. This issue may result in added re-work and increased delays due to the lead time needed to obtain additional clock frequencies.


Traditional Frequency Flexible XOs Do Not Meet the Challenge

A better approach to the problem of performing frequency margining is to use in-circuit programmable XOs that can generate a continuum of frequencies with very high incremental frequency resolution without introducing phase glitching or compromising phase jitter
performance.

To address this need, traditional XO suppliers use analog circuit techniques such as phase locked loops (PLLs) to overcome the frequency rigidity of conventional crystal oscillators.
However, analog PLLs are often limited to powers-of-two or integer frequency multiplication.

These solutions cannot meet the frequency resolution required to provide the designer with total
frequency programming or "tuning" flexibility.

Power Supply Rejection Performance Also Affects System Prototyping and Debug Time

Analog PLLs are notoriously sensitive to noise, often coupling and amplifying noise sources through the power supply and internal VCO to the output clock signal. This sensitivity prevents
analog PLLs from driving ultra-low jitter clock signals in high-performance systems where clocking flexibility is important and the environment tends to be noisy and hostile.

The system noise is largely due to transient load switching currents and the widespread use of switch mode power supplies (SMPS) in most computer, communications and consumer systems.

Integrated filtering and regulation translates directly into a BOM cost and component count savings since designers can minimize or even eliminate external power supply filters and ferrite bead components needed to maintain adequate jitter performance. For example, assume a
100 mVpp sinusoidal ripple over a range of 100 kHz to 1 MHz is present on the power supply of an analog PLL-based XO. Switching power supplies necessary to improve system power
efficiency commonly operate over this frequency range.

I2C Digitally-Programmable XOs Offer a Versatile Solution

I2C digitally-programmable XOs provide a flexible alternative to fixed-frequency XOs. For example, as shown in Figure 2, Silicon Labs’ programmable oscillators combine a traditional fixed-frequency crystal reference and patented DSPLL technology to provide an I2C
programmable output with adjustable frequency resolution better than 26 parts per trillion.

Because of their unique digital circuitry and extensive internal power supply regulation filtering, oscillators based on DSPLL technology easily achieve jitter performance comparable to fixed
frequency SAW-based oscillators.


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